Wide gap semiconductor materials are excellent in dielectric breakdown electric field strength, about 10 times as high as that of silicon, and receive attention as a material suited for high withstand voltage power semiconductor devices having high withstand voltage characteristics.
Bipolar semiconductor devices such as pn-diodes, bipolar transistors, GTO and GCT have a higher built-in voltage than unipolar semiconductor devices such as Schottky diodes and MOSFET, but have a resistance that is greatly lowered by the conductivity modulation of a drift layer caused by minority carrier injection. Therefore, in the field of high voltage and high current such as power application, the bipolar semiconductor devices are used to reduce power loss.
When these bipolar semiconductor devices are made of SiC, extraordinarily excellent performance can be attained as compared with Si devices. For example, a SiC pn-diode with a withstand voltage of 10 kV provides various advantages over a pn-diode made of Si; that is, the forward voltage is about ⅓, the reverse recovery time that corresponds to an off-time speed is about 1/20 or less, and the power loss is about ⅕ or lower as compared with a Si pn-diode, thereby greatly contributing to energy saving.
Reduction in power loss has been also reported for SiC bipolar devices other than the SiC pn-diodes, such as SiC npn-transistors, SiC SIAFET and SiC SIJFET (Non-Patent Document 1). Besides these devices, SiC GTO having as a drift layer a p-type semiconductor layer with a reverse polarity has also been disclosed (Non-Patent Document 2).
As a conventional pn-diode using SiC, there may be mentioned a high voltage diode with a planar structure as shown in FIG. 14 (Non-Patent Document 3). The withstand voltage of this pn-diode is about 3.4 kV. In this pn-diode, a SiC single crystal n+ substrate 1 has a cathode 5 on one face thereof, a n-type drift layer 2 is formed on the other face of the substrate, and a p-type carrier injection layer 3 is formed at a central part of the n-type drift layer 2. On both sides of the p-type carrier injection layer 3, a p-type layer 51 for termination is formed.
The “termination” in a high voltage semiconductor device denotes various kinds of semiconductor layers that are formed around a pn-junction through which a current flows, to reduce the electric field concentration around the pn-junction in a reverse biasing. In the pn-diode shown in FIG. 14, the pn-junction through which a current flows and the pn-junction between the termination p-type layer 51 which reduces the electric-field concentration and the n-type drift layer 2 are formed by ion implantation of boron, aluminum or the like.
As another example of the high voltage diodes using SiC, there may be mentioned a diode with a structure shown in FIG. 15 (Non-Patent Document 4). The withstand voltage of this pn-diode is 8.3 kV. In this pn-diode, the pn-junction between a p-type carrier injection layer 3 which injects carriers to a n-type drift layer 2 and the n-type drift layer 2 is formed by epitaxial growth, and then a mesa structure is formed by reactive ion etching to perform device separation.
To form the mesa structure in this pn-diode, both ends of a p-type carrier injection layer 3 that is formed in about 2 μm thickness on the entire surface of a n-type drift layer 2 are mesa-etched to a depth of 4 μm. After the mesa structure is formed, a p-type layer 52 for termination which reduces the electric field concentration is formed. The surface of the device is protected with a silicon dioxide layer (passivation layer 4) except a portion where an anode 6 is formed.
Non-Patent-Document 1: “Handoutai SiC Gijutsu To Ouyou (Semiconductor SiC technology and applications)” edited and written by Matsunami Hiroyuki, pages 218 to 221, published by THE NIKKAN KOGYO SHIMBUN, LTD, Mar. 31, 2003;
Non-Patent Document 2: Materials Science Forum, Volumes 389 to 393, pages 1349 to 1352, year 2000;
Non-Patent Document 3: Extended Abstracts of International Conference on Silicon Carbide, III-Nitride and Related Materials, pages 136 to 137, year 1997;
Non-Patent Document 4: Materials Science Forum, Volumes 483 to 485, pages 969 to 972, year 2005;
Non-Patent Document 5: Journal of Applied Physics, Volume 95, No. 3, pages 1485 to 1488, year 2004;
Non-Patent Document 6: Journal of Applied Physics, Volume 92, No. 8, pages 4699 to 4704, year 2004; and
Non-Patent Document 7: Journal of Crystal Growth, Volume 262, pages 130 to 138, year 2004.